2017

  • J. Lee, H. Kim, S. Yoo, K. Choi, P. Hofstee, G. Nam, M. Nutter, D. Jamsek, "ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator," to appear in Proc. International Conference on Very Large Database (VLDB), Aug. 2017.
  • E. Park, J. Ahn, S. Yoo, "Weighted Entropy-based Quantization for Deep Neural Networks," Proc. IEEE Conference on Computer Vision and Pattern Recognition (CVPR), July 2017.
  • M. Son, H. Park, J. Ahn, S. Yoo, "Making DRAM Stronger Against Row Hammering," Proc. Design Automation Conference (DAC), June 2017.
  • D. Kim, J. Ahn, S. Yoo, "A Novel Zero Weight/Activation-Aware Hardware Architecture of Convolutional Neural Network," Proc. Design Automation and Test in Europe (DATE), March 2017.

2016

  • J. Koo, E. Song, E. Park, D. Kim, J. Park, S. Ryu, S. Yoo, J. Kim, "Area-Efficient One-Cycle Correction Scheme for Timing Errors in Flip-Flop Based Pipelines," Proc. IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2016.
  • T. Lee, S. Yoo, "Selective Refresh to Avoid Read Disturb Errors in STT-RAM Main Memory," Proc. IEEE International SoC Design Conference (ISOCC), Oct. 2016.
  • H. Park, D. Kim, J. Ahn, S. Yoo, "Zero and Data Reuse-aware Fast Convolution for Deep Neural Networks on GPU," Proc. CODES+ISSS, Oct. 2016.
  • Y. Kim, E. Park, S. Yoo, T. Lee, L. Yang, D. Shin, "Compression of Deep Convolutional Neural Networks for Fast and Low Power Applications," Proc. International Conference on Learning and Representation (ICLR), May 2016.

2015

  • H. Park, J. Ahn, E. Park, S. Yoo, "Locality-Aware Vertex scheduling for GPU-Based Graph Computation," Proc. VLSI-SOC, Oct. 2015.
  • H. Park, C. Kim, S. Yoo, C. Park, "Filtering Dirty Data In-DRAM to Reduce PRAM Writes," Proc. VLSI-SOC, Oct. 2015.
  • E. Park, D. Kim, S. Kim, Y. Kim, S. Yoon, G. Kim, S. Yoo, "Big/Little Deep Neural Network for Ultra Low Power Inference," Proc. CODES+ISSS, Oct. 2015.
  • M. Son, J. Ahn, S. Yoo, "A Tiny-Capacitor-backed Non-volatile Buffer to Reduce Storage Writes in Smartphone," Proc. CODES+ISSS, Oct. 2015.
  • D. Lee, D. Kim, S. Yoo, "An Arrayed-Range-Gate Data Acquisition for Spatial Distribution Analysis of Myocardial Tissue Vibration from Stenosis in Coronary Doppler Vibrometry," Proc. IUS (International Ultrasonics Symposium), Oct. 2015.
  • J. Ahn, S. Yoo, O. Mutlu, K. Choi, "PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture," Proc. International Symposium on Computer Architecture (ISCA), June 2015.
  • J. Ahn, S. Hong, S. Yoo, O. Mutlu, K. Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing," Proc. International Symposium on Computer Architecture (ISCA), June 2015.
    One of the 23 computer architecture papers of 2015 selected as Top Picks (Honorable Mention) by IEEE Micro.
  • E. Park, J. Ahn, S. Hong, S. Yoo, S. Lee, "Memory Fast-Forward, A Low Cost Special Function Unit to Enhance Energy Efficiency in GPU for Big Data Processing," Proc. Design Automation and Test in Europe (DATE), March 2015.
  • M. Son, S. Lee, K. Kim, S. Yoo, S. Lee, "A Small Non-Volatile Write Buffer to Reduce Storage Writes in Smartphones," Proc. Design Automation and Test in Europe (DATE), March 2015.

2014

  • T. Lee, H. Park, D. Kim, S. Yoo, S. Lee, "FPGA-based Prototyping Systems for Emerging Memory Technologies," Proc. Rapid System Prototyping, Oct. 2014.
  • D. Lee, S. Yoo, et al., "An Interleaved Data Acquisition to Reduce Common Noise in Coronary Doppler Vibrometry", Proc. International Ultrasound Symposium (IUS), Sept. 2014.
  • J. Ahn, S. Yoo, K. Choi, "Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes," Proc. Design Automation Conference (DAC), June 2014.
  • E. Park, S. Yoo, H. Li, S. Lee, "Accelerating Graph Computation with Racetrack Memory and Pointer-Assisted Graph Representation," Proc. Design Automation and Test in Europe (DATE), March 2014.
  • H. Kim, D. Kim, J. Kim, S. Yoo, S. Lee, "Coarse-grained Bubble Razor to Exploit the Potential of Two-Phase Transparent Latch Designs," Proc. Design Automation and Test in Europe (DATE), March 2014.
  • J. Ahn, S. Yoo, K. Choi, "DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture", Proc. High Performance Computer Architecture (HPCA), Feb. 2014.

2013

  • J. Ahn, S. Yoo, K. Choi, "Write Intensity Prediction for Energy-Efficient Non-Volatile Caches," Proc. International Symposium on Low Power Electronic Design (ISLPED), Sept. 2013.
  • J. Park, S. Yoo, J. Lee, et al., "Fast Coronary Doppler Vibrometry to Detect Myocardial Vibration Associated with Coronary Artery Stenosis Using Flash Imaging," Proc. IEEE International Ultrasonics Symposium (IUS), July 2013.
  • J. Ahn, K. Choi, S. Yoo, "Selectively Protecting Error-Correcting Code for Area-Efficient and Reliable STT-RAM Caches," Proc. Asia-South Pacific Design Automation Conference (ASPDAC), Jan. 2013.
  • S. Kang, S. Cho, S. Yoo, Y. Kim, "Multi-histogram based scene change detection for frame rate up-conversion," Proc. International Conference on Consumer Electronics (ICCE), Jan. 2013.

2012

  • D. Kim, S. Lee, J. Chung, D. Kim, D. Woo, S. Yoo, S. Lee, "Hybrid DRAM/PRAM-based Main Memory for Single-Chip CPU/GPU," Proc. DAC, June 2012.
  • Y. Kim, S. Yoo, S. Lee, "Write Performance Improvement by Hiding R Drift Latency in Phase-Change RAM," Proc. DAC, June 2012.
  • S. Kwon, D. Kim, Y. Kim, S. Yoo, S. Lee, "A Case Study on the Application of Real Phase-Change RAM to Main Memory Subsystem," Proc. DATE, 2012.
  • J. Yun, S. Yoo, S. Lee, "Bloom Filter-based Dynamic Wear Leveling for Phase Change RAM," Proc. DATE, 2012.
  • C. Kim, S. Yoo, S. Lee, P. Kang, C. Park, W. Chang, "Gradual Error Correction Code to Extend the Lifetime of Flash Memory," Proc. Non-Volatile Memory Workshop, March 2012.

2011

  • Y. Kim, S. Yoo, S. Lee, "Non-volatile Memory-Aware Cache Replacement Policy," Proc. MeAOW, 2011.
  • S. Lee, S. Yoo, S. Lee, "Reducing Read Latency in Phase-Change RAM-based Main Memory," Proc. MWSCAS, 2011.
  • K. Kang, J. Jung, S. Yoo, C. Kyung, "Integration of Cache Data Allocation and Voltage/Frequency Scaling for Temperature Constrained Multi-core Systems with 3-D Stacked Cache Memory," Proc. MWSCAS, 2011.
  • Y. Choi, S. Yoo, S. Lee, "Matching Cache Access Behavior and Bit Error Pattern for High Performance Low Vcc L1 Cache," Proc. DAC, 2011.
  • H. Park, S. Yoo, S. Lee, "Power Management of Hybrid DRAM/PRAM-based Main Memory," Proc. DAC, 2011. (Best Paper Award Nomination)
  • K. Kim, J. Kim, S. Yoo, "FlexiBuffer: Reducing Leakage Power in On-Chip Network Routers," Proc. DAC, 2011.
  • K. Kang, J. Jung, S. Yoo, C. Kyung, "Maximizing Throughput of Temperature-Constrained Multi-Core Systems with 3D-Stacked Cache Memory," Proc. ISQED, 2011.
  • H. Park, S. Yoo, S. Lee, Y. Cho, "A Novel Tag Access Scheme for Low Power L2 Cache," Proc. DATE, 2011.
  • D. Kim, S. Yoo, S. Lee, J. Ahn, H. Jung, "A Quantitative Analysis of Performance Benefits of 3D Die Stacking on Mobile and Embedded SoC," Proc. DATE, 2011.

2010

  • J. Kim, Y. Lee, S. Yoo, C. M. Kyung, "An Analytical Dynamic Scaling of Supply Voltage and Body Bias Exploiting Memory Stall Time Variation," Proc. ASPDAC, Jan. 2010.
  • D. Kim, S. Yoo, S. Lee, "A Network Congestion-Aware Memory Controller," Proc. Network-on-Chip Symposium, May 2010. (Acceptance ratio = 26%)
  • J. Kim, J. Kim, G. Kim, S. Na, S. Yoo and C. Kyung, "Event Statistics and Criticality-Aware Bitrate Allocation to Minimize Energy Consumption of Memory-Concentrated Wireless Surveillance System," IEEE International Conference on Multimedia & Expo (ICME), July 2010. (Regular paper acceptance rate 15%)
  • A. Tran, S. Yoo, S. Lee, and C. Park, "Memory-Mapped Invert Coding for PRAM Main Memory," presented at EMT (emerging memory technology) workshop co-located with ISCA, June 2010.

2009

  • J. Park, S. Yoo, C. Park, and S. Lee, "Power Modeling of Solid State Disk for Dynamic Power Management Policy Design in Embedded Systems,’ Proc. the Seventh IFIP Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS), 2009.
  • J. Yoo, S. Yoo, K. Choi, "Multiprocessor System-On-Chip Designs with Active Memory Processors for Higher Memory Efficiency," Proc. DAC, 2009.
  • W. Kwon and S. Yoo, "In-Network Reorder Buffer To Improve NoC Performance While Resolving the In-Order Requirement Problem," Proc. DATE, 2009.
  • J. Kim, S. Yoo, C. Kyung, "Program Phase and Runtime Distribution-Aware Online DVFS for Combined Vdd/Vbb Scaling," Proc. DATE, 2009.

2008

  • S. Oh, J. Kim, S. Hong, S. Yoo, C. Kyung, "Profile-based Workload Prediction Method for Dynamic Voltage and Frequency Scaling in Multiprocessor Embedded System," Proc. VLSI-SOC, 2008.
  • D. Lee, S. Yoo, K. Choi, "Entry Control in Network-on-Chip for Memory Power Reduction," Proc. ISLPED, 2008.
  • W. Kwon, S. Yoo, S. Hong, B. Min, K. Choi, S. Eo, "A Practical Approach of Memory Access Parallelization to Exploit Multiple Off-chip DDR Memories," Proc. DAC, 2008.
  • W. Kwon, S. Hong, S. Yoo, B. Min, K. Choi, S. Eo, "An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication," Proc. DATE, 2008.
  • S. Hong, S. Yoo, B. Min, K. Choi, S. Eo, T. Kim, "Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution," Proc. DATE, 2008.
  • S. Eo, S. Yoo, K. Choi, "An Industrial Perspective of Power-aware Reliable SoC Design," Proc. ASPDAC, Jan. 2008.
  • M. Jeon, S. Yoo, and E. Chung, "Mixed Integer Linear Programming-based Optimal Topology Synthesis of Cascaded Crossbar Switches," Proc. ASPDAC, Jan. 2008.

2007

  • I. Lee, S. Yoo, H. Jin, K. Choi, S. Eo, "Task-level dynamic power management: Commercial mobile application processor case study," Proc. ISOCC, Oct. 2007.
  • J. Liu, S. Yoo, H. Jin, K. Choi, S. Eo, "Register Slice Optimization for the AXI Bus Design," Proc. ISOCC, Oct. 2007. (Best Paper Bronze Prize)
  • J. Yoo, D. Lee, S. Yoo, and K. Choi, "Communication Architecture Synthesis of Cascaded Bus Matrix," Proc. Asia South Pacific Design Automation Conference (ASPDAC), Jan. 2007.

2006

  • S. Hong, S. Yoo, H. Jin, K. Choi, J. Kong, and S. Eo, "Runtime Distribution-Aware Dynamic Voltage Scaling," Proc. International Conference on Computer-Aided Design (ICCAD), Nov. 2006.
  • S. Hong, S. Yoo, S. Lee, S. Lee, H. Nam, B. Yoo, J. Hwang, D. Song, J. Kim, J. Kim, H. Jin, K. Choi, J. Kong, and S. Eo, "Creation and Utilization of a Virtual Platform for Embedded Software Optimization: An Industrial Case Study," Proc. International Symposium on Hardware-Software Codesign and System Synthesis (CODES-ISSS), Oct. 2006.
  • I. Lee, H.Kim, P. Yang, S. Yoo, E. Chung, K. Choi, J. Kong, and S. Eo, "PowerViP: SoC Power Estimation Framework at Transaction Level," Proc. ASPDAC, Jan. 2006.

2005

  • H. Kim, S. Kim, S. Yoo, E. Chung, K. Choi, J. Kong, and S. Eo, "An Industrial Case Study of the ARM926EJ-S Power Modeling," Proc. International SoC Design Conference (ISOCC), Oct. 2005. (Best Paper)
  • Y. Cho, S. Yoo. K. Choi, N. Zergainoh, and A.A. Jerraya, "Scheduler implementation in MPSoC design," Proc. ASPDAC, pp.151-156, Jan. 2005

2004

  • M. Youssef, S. Yoo, A. Sasongo, Y. Paviot, and A. A. Jerraya, "Debugging HW/SW Interface for MPSoC: Video Encoder System Design Case Study," Proc. Design Automation Conference (DAC), June 2004.
  • S. Yoo, M. Youssef, A. Bouchhima, A. A. Jerraya, and M. Diaz-Nava, "Multi-Processor SoC Design Methodology using a Concept of Two-Layer Hardware-dependent Software," Proc. Design, Automation, and Test in Europe (DATE), Feb. 2004.
  • A. Bouchhima, S. Yoo, and A. Jerraya, "Fast and Accurate Timed Execution of High Level Embedded Software using HW/SW Interface Simulation Model," Proc. ASPDAC, Jan. 2004.

2003

  • Y. Cho, S. Yoo, and K. Choi, "Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design," Proc. DATE 2003.
  • S. Yoo, A. Bouchhima, I. Bacivarov, and A. A. Jerraya, "Building Fast and Accurate SW Simulation Models based on SoC Hardware Abstraction Layer and Simulation Environment Abstraction Layer," Proc. DATE 2003.

2002

  • I. Bacivarov, S. Yoo, and A. A. Jerraya, "Timed HW-SW Cosimulation Using Native Execution of OS and Application SW," Proc. IEEE International High Level Design Validation and Test Workshop (HLDVT), Oct. 2002.
  • G. Nicolescu, S. Yoo, and A. A. Jerraya, "Validation in a Component-Based Design Flow for Multicore SoCs," Proc. International Symposium on System Synthesis", Proc. International Symposium on System Synthesis (ISSS), Japan, Oct. 2002.
  • S. Lee, S. Yoo, and K. Choi, "An Intra-Task Dynamic Voltage Scaling Method for SoC Design with Hierarchical FSM with Synchronous Dataflow Model," Proc. International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2002.
  • W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A. A. Jerraya, and M. Diaz-Nava, "Component-Based Design Approach for Multicore SoCs," Proc. DAC, June 2002.
  • S. Lee, S. Yoo, and K. Choi, "Reconfigurable SoC design with Hierarchical FSM and Synchronous Dataflow Model," Proc. CODES, May 2002.
  • S. Yoo, G. Nicolescu, L. Gauthier and A. A. Jerraya, "Automatic Generation of Fast Timed Simulation Models for OS in SoC Design," Proc. DATE, Mar. 2002. (Best Paper Candidate)
  • W. Cesario, Y. Paviot, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, S. Yoo and A. A. Jerraya, "HW/SW Interfaces Design of a VDSL Modem Using Automatic Refinement of a Virtual Architecture Specification into A Multiprocessor SoC: A Case Study," Designer's Forum, DATE, Mar. 2002.
  • Y. Ahn, D. Kim, S. Yoo, and K. Choi, "An Efficient Simulation Environment for the Design of Networked Bluetooth Devices," Designer's Forum, DATE, Mar. 2002.
  • G. Nicolescu, S. Martinez, L. Kriaa, W. Youssef, S. Yoo, B. Charlot and A. A. Jerraya, "Application of Multi-domain and Multi-language Cosimulation to an Optical MEM Switch Design," Proc. 7th ASP-DAC & 15th ICVD, Jan. 2002.

2001

  • Y. Ahn, D. Kim, S. Lee, S. Park, S. Yoo, K. Choi, and S. Chae, "An efficient simulation environment for the design of networked bluetooth devices," SOC Design Conference, pp.622-628, 2001.
  • S. Yoo, G. Nicolescu, L. Gauthier and A. A. Jerraya, "Fast Timed Cosimulation of HW/SW Implementation of Embedded Multiprocessor SoC Communication," Proc. HLDVT, Nov. 2001.
  • L. Gauthier, S. Yoo, and A. A. Jerraya, "Application-Specific Operating Systems Generation and Targeting for Embedded SoCs," Proc. SASIMI, 2001.
  • D. Lyonnard, S. Yoo, A. Baghdadi, and A. A. Jerraya, "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip," Proc. DAC, Las Vegas, June 2001.
  • S. Yoo, G. Nicolescu, D. Lyonnard, A. Baghdadi, and A. A. Jerraya, "A Generic Wrapper Architecture for Multi-Processor SoC Cosimulation and Design," Proc. CODES, Copenhagen, April 2001.
  • L. Gauthier, S. Yoo, and A. A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software," Proc. 5th Int'l Workshop on Software and Compilers for Embedded Systems (SCOPES), March 2001.
  • L. Gauthier, S. Yoo, and A. A. Jerraya, "Automatic Generation and Targeting of Application Specific Operating Systems and Embedded Systems Software," Proc. DATE, March 2001.
  • J. Jung, S. Yoo, and K. Choi, "SW Analysis-based Performance Improvement of Multi-Processor Systems," Proc. DATE, March 2001.
  • G. Nicolescu, S. Yoo, and A. A. Jerraya, "Mixed-Level Cosimulation for Fine Gradual Refinement of Communication in SoC Design," Proc. DATE, March 2001.
  • P. Gerin, S. Yoo, G. Nicolescu and A. A. Jerraya, "Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-Processor Target Architectures," Proc. ASPDAC, Yokohama, Jan. 2001.

~2000

  • S. Yoo, K. Rha, Y. Cho, J. Jung, and K. Choi, "Performance Estimation of Multiple-Cache IP based Systems: Case Study of an Interdependency Problem and Application of an Extended Shared Memory Model," Proc. CODES, May 2000.
  • S. Yoo, J. Lee, J. Jung, K. Rha, Y. Cho, and K. Choi, "Fast Hardware-Software Coverification by Optimistic Execution of Real Processor," Proc. DATE, Paris, March 2000.
  • B. Jeong, S. Yoo, S. Lee and K. Choi, "Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs," Proc. ASPDAC, Jan. 2000.
  • S. Yoo, J. Lee, J Jeong, K. Na, Y. Cho and K. Choi, "Fast Prototyping of an IS-95 CDMA Cellular Phone : a Case Study," Proc. Asia-Pacific Chip Design Language conference (APCHDL), Japan, Oct. 1999.
  • S. Yoo and K. Choi, "Interleaving Partial Bus Invert Coding for Low Power Reconfiguration of FPGAs," Proc. International Conference on VLSI and CAD (ICVC), Oct. Korea, 1999.
  • S. Yoo and K. Choi, "Optimizing Geographically Distributed Timed Cosimulation by Hierarchically Grouped Messages," Proc. CODES, Rome, Italy, May 1999.
  • B. Jeong, S. Yoo and K. Choi, "Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design," A poster presentation at the Seventh ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), Monterey, USA, Feb. 1999.
  • S. Yoo and K. Choi, "Optimistic Distributed Timed Cosimulation Based on Thread Simulation Model," Proc. CODES, Seattle, USA, Mar. 1998.
  • S. Yoo and K. Choi, "Synchronization Overhead Reduction in Timed Cosimulation," Proc. HLDVT, Berkeley, USA, Nov. 1997.
  • S. Yoo and K. Choi, "Optimistic Timed HW-SW Cosimulation," Proc. APCHDL, Hsinchu, Taiwan, Aug. 1997.
  • S. Yoo, J. Jeon, S. Hong, and K. Choi, "Hardware-software codesign of resource constrained real-time systems," Proc. IEEE International Workshop on Real-Time Computing Systems and Applications (RTCSA), Seoul, Korea, Oct. 1996.
  • S. Yoo and K. Choi, "High performance FPGA interconnect delay estimation," Proc. Canadian Workshop on Field Programmable Devices, Toronto, Canada, May 1996.