Deep learning hardware accelerator
Recently, hardware acceleration of neural networks started to be applied to both servers, e.g., Google’s TPU and mobile devices, e.g., Huawei and Apple’s NPUs. We aim at devising accelerator architectures which offer orders of magnitude larger performance/area-watt than the current accelerators. Especially, our goal in training is 100X smaller memory and 5X faster computation. We will achieve this by co-design of algorithm (e.g., quantization-aware network architectures and training methods), software (dynamic quantization methods) and hardware (accelerators supporting zero skipping [D&T2017] and extremely low precision).
[D&T2017] D. Kim, J. Ahn, S. Yoo, "ZeNA: Zero-Aware Neural Network Accelerator," accepted for publication in Special Issue on Hardware Accelerators for Data Centers, IEEE Design & Test, 2017.